1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device provided with a trench isolation, particularly to a method of fabricating a semiconductor device capable of reducing an inverse narrow channel effect in which a threshold voltage lowers as the channel width of a transistor decreases in a metal oxide semiconductor field effect transistor (MOSFET).
2. Description of the Related Art
Referring to FIG. 1A, description will be made about a conventional method of fabricating a semiconductor device. A trench 103 is first formed on a single-crystal silicon substrate 101, then the inner surfaces of the trench 103 are entirely oxidized through the chemical vapor deposition (CVD) method, and silicon oxide 105 is piled up as shown in FIG. 1A.
Then, as shown in FIG. 1B, the silicon oxide 105 on the surface is polished and smoothed through the chemical mechanical polishing (CMP) method and thereby, the trench 103 is filled with the silicon oxide 105, and then the surface of the silicon oxide 105 and the principal surface of the single-crystal silicon substrate 101 are covered with a gate insulating film 111 to be formed between the silicon oxide 105 and a gate electrode 110.
In this case, when the silicon oxide 105 filling the bottom of the trench 103 is lower than the principal surface of the single-crystal silicon substrate 101 as shown in FIG. 1B, a problem occurs that the threshold voltage of a MOSFET lowers by approx. 0.15 V if the channel width of the MOSFET decreases to 0.2 .mu.m from 10 .mu.m as shown by the characteristic diagram in FIG. 1C.
This is because, as described, for example, in IEDM (International Electron Devices Meeting) in 1981, Technical Digest (pp. 380-383), an electric field V in the internal direction of the single-crystal silicon substrate 101 from the gate electrode 110 and an electric field H in the direction parallel with the surface are concentrated nearby a trench shoulder 112 and then the threshold voltage of the trench shoulder 112 lowers.
That is, when the channel width of a MOSFET decreases, the rate of the portion where the threshold voltage lowers to the entire channel increases and the threshold voltage of the entire MOSFET also lowers.
To solve the above problem, there is a method of raising the threshold voltage of an edge portion of the semiconductor device by implanting impurity ions from the side surfaces of a trench.
However, because the impurity concentration becomes higher than that in the single-crystal silicon substrate 101 in the vicinity of the interface between the single-crystal silicon substrate 101 and an oxide film filling the trench 103, a junction capacity and a junction leak current are increased.
To avoid the above problem, as described in Japanese Unexamined Patent Publication No. 6-177239 (177239/1998) for example, there is a method of forming a tapered trench by etching a separation region of the semiconductor device, that is, a method of controlling the concentration of electric fields by preventing a shoulder shape from being formed at an edge portion of a semiconductor device or chamfering a shoulder.
In the case of the above conventional method of fabricating a semiconductor device, there is a problem that a phenomenon due to the inverse narrow channel effect occurs in which a threshold voltage lowers when the channel width of a transistor is too small even if using the method of controlling the concentration of electric fields by preventing a shoulder shape from being formed at an edge portion of the semiconductor device or chamfering a shoulder.
This is because the boron contained in a channel is piled up on the silicon oxide side filling a trench at the interface between the silicon of a substrate and the silicon oxide due to thermal diffusion and thereby, it diffuses outward, and a region in which the boron concentration lowers is formed nearby the interface between the trench and the substrate. The boron diffusion occurs even at approx. 800.degree. C. because inter-grid silicon is present which is produced due to ion implantation or the like.
Moreover, because phosphorus or arsenic serving as an impurity for forming an n-well is piled up on the silicon side of a substrate, it does not diffuse outward from a channel. Therefore, the above phenomenon does not occur.